3.2.1 Definition of Chip and Cluster Specifications for Model Training
Original Problem in the Paper
Paper motivation: compute governance can target advanced AI because training/deployment requires large compute, but blunt chip restrictions risk overbreadth. Dedicated open problems: derive metrics/specs capturing chips/clusters relevant to AI while excluding ordinary compute; understand how throughput, memory bandwidth/capacity, and interconnect bandwidth affect suitability; close loopholes like downgraded chips still useful for AI; understand decentralized training and efficiency/cost of many small clusters/chips versus fewer powerful ones.
July 2026 Update & Trajectory
Policy has operationalized chip definitions using TPP/performance density, HBM controls, data-center authorizations, and 2026 entity-headquarters guidance. Technical work has made decentralized/low-communication training more feasible. But the scientific problem remains only narrowly operationalized: export-control metrics are proxies, still need continual revision, do not fully encode cluster/network/software stack suitability, and decentralized training progress creates new governance gaps.
Deployed / Operationalized
- BIS advanced-computing ECCNs classify AI chips by total processing performance and performance density, with notes covering GPUs, TPUs, neural processors, accelerators, FPGAs, and ASICs.
- BIS added/refined HBM and data-center/validated-end-user controls, acknowledging memory bandwidth/capacity and cluster/data-center context matter for advanced AI.
- BIS May 31 2026 guidance clarifies licenses remain required for advanced computing items to entities headquartered in Country Group D:5 or Macau even when located elsewhere.
- DiLoCo/OpenDiLoCo operationalize distributed low-communication training across poorly connected or geographically distributed clusters, indicating cluster-size/geography assumptions are less stable.
New Tractable Vectors
- Map export-control thresholds to commercially available accelerators and HBM stacks using TPP, performance density, memory bandwidth density, and .z-item containment.
- Study global/distributed training efficiency using open DiLoCo/Hivemind implementations across continents and countries.
- Assess compliance and diversion risk at data-center/customer-entity level, not only chip SKU level.
- Compare many-smaller-chip clusters versus fewer high-end GPUs under communication-efficient algorithms.
Key Open Questions
- Specification that robustly captures frontier-training suitability across compute, HBM, interconnect, topology, sparsity/quantization, compiler/runtime, and energy/cooling constraints.
- Governance thresholds that remain effective as vendors optimize just below TPP/performance-density cutoffs.
- Detecting and attributing decentralized training runs split across regions, accounts, providers, and chip classes.
- Quantifying when inference clusters or post-training/fine-tuning clusters become strategically equivalent to pretraining compute.
- International harmonization and auditability of data-center controls without blocking benign scientific/business workloads.
Evidence & Primary Sources
- Framework for Artificial Intelligence Diffusion rule revised advanced-computing IC controls and added model-weight controls; ECCN 3A090 thresholds use total processing performance and performance density (e.g., 4800 TPP; 1600 TPP plus 5.92 density; 2400-4800 with density ranges). (2025-01-15): https://www.federalregister.gov/documents/2025/01/15/2025-00636/framework-for-artificial-intelligence-diffusion
- December 2024 BIS rule added controls for HBM because HBM provides memory capacity/bandwidth needed for advanced AI models and supercomputing applications. (2024-12-05): https://www.federalregister.gov/documents/2024/12/05/2024-28270/foreign-produced-direct-product-rule-additions-and-refinements-to-controls-for-advanced-computing
- BIS January 2025 due-diligence rule states earlier controls adjusted parameters for advanced-computing ICs critical to AI and imposed measures addressing circumvention risk. (2025-01-16): https://www.federalregister.gov/documents/2025/01/16/2025-00711/implementation-of-additional-due-diligence-measures-for-advanced-computing-integrated-circuits
- BIS May 31 2026 guidance confirms license requirements for advanced computing items including ECCNs 3A090/4A090 and related .z items for D:5/Macau-headquartered entities; FAQ updated June 17 2026. (2026-05-31): https://www.bis.gov/media/documents/bis-guidance-may-31-2026.pdf
- DiLoCo enables LLM training on poorly connected device islands, matching fully synchronous optimization on 8 workers while communicating 500x less; revised version published September 2024. (2024-09-23): https://arxiv.org/abs/2311.08105
- OpenDiLoCo trained across two continents and three countries with 90-95% compute utilization and scaled to billion-parameter models. (2024-07-10): https://arxiv.org/abs/2407.07852